A CMOS output stage or any prior stage has certain physical and electrical limitations. Many of these limitations can be overcome with the use of a buried power buss.
Overview of Issues Limiting the CMOS
FIG. 1 is a cross-section of a conventional CMOS device 10 utilized as a power output stage. The CMOS device 10 is a dual well device P well 12 and N well 14 with appropriate N and P regions therein 16 and 18. The CMOS device 10 includes a ground 20 which is coupled to the P well 12 and the N doped section 16, a power out connection 22, an N doped region 16, the P well doped region 18 of the N doped region and a power connection 24 to the P doped region of the N well.
The connections shown to the output stage are typical of the earlier stages of a CMOS device, the main difference being the amount of current and the resultant power that this output stage carries. Because of the high current demand the output stage differs from the other stages by the W/L ratio and the resultant larger size, as well as the amount of metal used. The various metal interconnects are the inputs, ground, the power buss, and the drains of the P channel and N channel tied together forming the output. Since the output stage must carry the highest current these metal interconnects need to have a much larger cross section than the earlier stages. This is to prevent electromigration, IR drops, chip heat, and in some cases reduce the time constant presented by this metal drop and the capacitance of the load and distributed capacitance of the metal interconnect itself.
There are many issues related to providing a CMOS output stage that has adequate performance. These issues include the following:
1. The dual well has a somewhat weak point where the two wells tend to merge. This can be a leaky area or an area of low breakdown. It can have a very low field threshold.
2. The N channel device has a parasitic NPN from the drain through the P well to the epitaxial layer. This can cause problems and is mainly determined by the distance the N drain is from the edge of the P well.
3. Also, the level of positive charge in the oxide above the drain/P well area can cause the region between the N drain and the edge of the P well to have a channel that can connect the N drain to the N epitaxial layer resulting in a short drain to the epitaxial layer.
4. The P channel device has a somewhat similar issue that usually does not come into the picture. The distance from the edge of the P drain to the edge of the N well is important since a short can result to the epitaxial area. Also it has a parasitic PNP from drain through the N well to the P substrate.
5. The N channel device has a parasitic NPN bipolar device made up of the source of the N channel, the P well, and the drain of the N channel (or the N epitaxial layer). Hole current is generated in the P well by impact ionization which flows out of the source of the N channel to ground. At some point the IR drop forward biases the source/P well junction and results in injection and the resulting NPN action. This results in a voltage and current limiting bipolar snap back voltage and sustaining current.
6. Current carrying capability is determined by the thickness, width and resistivity of the metal line interconnects. Except for the inputs of the power output stage the rest of the output interconnects must normally carry the same high current. Current is limited by current density which, if exceeded, can result in electromigration issues. This is very important for the power, ground, and output of the power output stage.
7. In cases where speed is desired the resistance in the poly or metal interconnect leads can result in RC time constant limitations. This RC time constant relates to the distributed resistance capacitance of the interconnects and the capacitance of the inputs or loads the lead is connecting to.
8. Current is determined by the uCW/L of the device as well as the gate voltage that drives the device. Current can be limited by insufficient voltage on the gate due to IR drops in the interconnect to the gates.
9. Heat is generated in the output stage as a result of the high current IR heating of the metal as well as power consumption of the output stage.
10. The on resistance (Ron) of the device is determined by several physical elements of the output stage as well as some related to the device physics. The sheet resistance of the metal, the length of the metal, the resistance of the ground connection, the turn on resistance of the device as a function of the drive to the device, the channel length, the contact resistance of the drain, and the mobility of the channel.
11. The Ron times area product of the device is a figure of merit that wants this to be as low as possible for the given function to be performed.
12. The speed/power factor of the device where the highest speed is desired at the lowest power for that given function. These issues are present in dual well or single well (CMOS) devices.
Accordingly, what is needed is a system and method which overcomes the above-identified issues. The present invention addresses and resolves these issues.